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features ? supply voltage up to 40v operating voltage v s = 5v to 27v typically 10 a supply cu rrent during sleep mode typically 57 a supply current in silent mode linear low-drop voltage regulator: ? normal, fail-safe, and silent mode ? ATA6623: v cc = 3.3v 2% ? ata6625: v cc = 5.0v 2% ? sleep mode: v cc is switched off v cc undervoltage detection wi th reset open drain outp ut nres (4 ms reset time) voltage regulator is short-circ uit and over-temperature protected lin physical layer according to lin sp ecification revision 2.0 and saej2602-2 wake-up capability via lin bus (90 s dominant) txd time-out timer bus pin is overtemperature and short-circuit protected versus gnd and battery advanced emc and esd performance esd hbm 8 kv at pins li n and vs following stm5.1 interference and damage prot ection according to iso/cd7637 package: so8 1. description ATA6623/ata6625 is a fully integrated lin transceiver, designed according to the lin specification 2.0, with a low-drop voltage regulator (3.3v/5v/50 ma). the combination of voltage regulator and bus transceiver makes it possible to develop simple, but pow- erful, slave nodes in lin bus systems. ATA6623/ata6625 is designed to handle the low-speed data communication in vehicles (f or example, in c onvenience electronics). improved slope control at the lin driver ensures secure data communication up to 20 kbaud with an rc oscillator for the protocol handling. the bus output is designed to withstand high voltage. sleep mode (vol tage regulator switched off) and silent mode (communication off; v cc voltage on) guarantee minimized current consumption. lin bus transceiver with integrated voltag e regulator ATA6623 ata6625 4957f?auto?02/08
2 4957f?auto?02/08 ATA6623/ata6625 figure 1-1. block diagram 2. pin configuration figure 2-1. pinning so8 3 gnd 2 en 6 txd 5 rxd vcc 8 nres 7 short circuit and overtemperature protection normal/silent/ fail-safe mode 3.3v/50 ma/2% 5v/50 ma/2% control unit normal and fail-safe mode rf-filter lin vs 1 4 txd time-out timer slew rate control undervoltage reset sleep mode vcc switched off wake-up bus timer ATA6623/25 receiver v cc - + v cc vcc 3 4 2 1 txd nres rxd vs 8 7 6 5 gnd en lin table 2-1. pin description pin symbol function 1 vs battery supply 2 en enables normal mode if the input is high 3 gnd ground, heat sink 4 lin lin bus line input/output 5 rxd receive data output 6 txd transmit data input 7 nres output undervoltage reset, low at reset 8 vcc output voltage regulator 3.3v/5v/50 ma
3 4957f?auto?02/08 ATA6623/ata6625 3. functional description 3.1 physical layer compatibility since the lin physical layer is independent from higher lin layers (e.g., lin protocol layer), all nodes with a lin physical layer according to revision 2.0 can be mixed with lin physical layer nodes, which are according to older versions (i.e., lin 1.0, lin 1.1, lin 1.2, lin 1.3) without any restrictions. 3.2 supply pin (vs) lin operating voltage is v s = 5v to 27v. an undervoltage detection is implemented to disable transmission if v s falls below 5v, in order to avoid false bus messages. after switching on v s , the ic starts with the fail-safe mode and the voltage regulator is switched on (i.e., 3.3v/5v/50 ma). the supply current in sleep mode is typi cally 10 a and 57 a in silent mode. 3.3 ground pin (gnd) the ic is neutral on the lin pin in the event of gnd disconnection. it is able to handle a ground shift up to 11.5% of v s . 3.4 voltage regulator output pin (vcc) the internal 3.3v/5v voltage regulator is c apable of driving loads with up to 50 ma, supplying the microcontroller and other ics on the pcb and is protected against overload by means of cur- rent limitation and overtemperature shut-down. furthermore, the output voltage is monitored and will cause a reset signal at the nres output pin if it drops below a defined threshold v thun . 3.5 undervoltage r eset output (nres) if the v cc voltage falls below the undervoltage detection threshold of v thun , nres switches to low after tres_f ( figure 6-1 on page 11 ). even if v cc = 0v the nres stays low, because it is internally driven from the v s voltage. if v s voltage ramps down, nres stays low until v s <1.5v and then becomes highly resistant. the implemented undervoltage delay keeps nres low for t reset = 4 ms after v cc reaches its nominal value. 3.6 bus pin (lin) a low-side driver with internal current limitation and thermal shutdown as well as an internal pull-up resistor according to lin specification 2.0 is implemented. the voltage range is from ?27v to +40v. this pin exhibits no reverse current from the lin bus to v s , even in the event of a gnd shift or v batt disconnection. the lin receiver thresholds are compatible with the lin proto- col specification. the fall time (from recessive to dominant) and the rise time (from dominant to recessive) are slope controlled.
4 4957f?auto?02/08 ATA6623/ata6625 3.7 input pin (txd) in normal mode the txd pin is the microcontroller interface to control the state of the lin output. txd must be pulled to ground in order to drive the lin bus low. if txd is high or unconnected (internal pull-up resistor), the lin output transisto r is turned off and the bus is in the recessive state. 3.8 dominant time-o ut function (txd) the txd input has an internal pull-up resistor. an internal timer prevents the bus line from being driven permanently in the dominant state. if txd is forced to low longer than t dom >6ms, the lin bus driver is switched to the recessive state. nevertheless, when switching to sleep mode, the actual level at the txd pin is relevant. to reactivate the lin bus driver, switch txd to high (> 10 s). 3.9 output pin (rxd) the pin reports the state of the lin-bus to the microcontroller. lin high (recessive state) is reported by a high level at rxd; lin low (dominant state) is reported by a low level at rxd. the output has an internal pull-up structure with typically 5 k ? to v cc . the ac characteristics are measured with an external load capacitor of 20 pf. the output is short-circuit protected. in unpowered mode (that is, v s = 0v), rxd is switched off. 3.10 enable input pin (en) this pin controls the operation mode of the interface. after power up of v s (battery), the ic switches to fail-safe mode, even if en is low or unconnected (internal pull-down resistor). if en is high, the interface is in normal mode. a falling edge at en while txd is still high forces the device to silent mode. a falling edge at en while txd is low forces the device to sleep mode.
5 4957f?auto?02/08 ATA6623/ata6625 4. mode of operation figure 4-1. mode of operation unpowered mode v batt = 0v a: v s > 5v b: v s < 4v c: bus wake-up event d: nres switches to low fail-safe mode normal mode vcc: 3.3v/5v/50 ma with undervoltage monitoring communication: on vcc : 3.3v/5v/50 ma with undervoltage monitoring communication : off silent mode vcc: 3.3v/5v/50 ma with undervoltage monitoring communication: off sleep mode vcc: switched off communication: off go to silent command a txd = 0 en = 0 txd = 1 en = 0 en = 1 en = 1 en = 1 b b b c + d d c b local wake-up event go to sleep command
6 4957f?auto?02/08 ATA6623/ata6625 4.1 normal mode this is the normal transmitting and receiving mode of the lin interface, in accordance with lin specification 2.0. the v cc voltage regulator operates with a 3.3v/5v output voltage, with a low tolerance of 2% and a maximum output current of 50 ma. if an undervoltage condition occurs, nres is s witched to low and the ic changes its state to fail-safe mode. all features are available. 4.2 silent mode a falling edge at en while txd is high switches the ic into silent mode. the txd signal has to be logic high during the mode select window ( figure 4-2 on page 7 ). the transmission path is disabled in silent mode. the overall supply current from v batt is a combination of the i vssi = 57 a plus the v cc regulator output current i vccs . the 3.3v/5v regulator with 2% tolerance can source up to 50 ma. in silent mode the internal slave termination between pin lin and pin vs is disabled to minimize the power dissipation in case pin lin is short-circuited to gnd. only a weak pull-up current (typically 10 a) between pin lin and pin vs is present. the silent mode can be activated independently from the current level on pin lin. if an undervoltage condition occurs, nres is switched to low and the ATA6623/ata6625 changes its state to fail-safe mode. a voltage less than the lin pre-wake detection v linl at pin lin activates the internal lin receiver. a falling edge at the lin pin followed by a dominant bus level maintained for a certain time period (t bus ) and the following rising edge at pin lin (see figure 4-3 on page 7 ) results in a remote wake-up request. the device switches from silent mode to fail-safe mode, then the internal lin slave termination resistor is swit ched on. the remote wake-up request is indicated by a low level at pin rxd to interrupt the microcontroller ( figure 4-3 on page 7 ). en high can be used to switch directly to normal mode. table 4-1. mode of operation mode of operation transceiver v cc rxd lin fail safe off 3.3v/5v high recessive normal on 3.3v/5v high txd depending silent off 3.3v/5v high recessive sleep off 0v 0v recessive
7 4957f?auto?02/08 ATA6623/ata6625 figure 4-2. switch to silent mode figure 4-3. lin wake-up waveform diagram from silent mode delay time silent mode t d _sleep = maximum 20 s mode select window lin switches directly to recessive mode t d = 3.2 s lin vcc nres txd en normal mode silent mode undervoltage detection active silent mode 3.3v/5v/50 ma fail-safe mode 3.3v/5v/50 ma normal mode low fail-safe mode normal mod e en high high nres en vcc rxd lin bus bus wake-up filtering time t bus
8 4957f?auto?02/08 ATA6623/ata6625 4.3 sleep mode a falling edge at en while txd is low switches the ic into sleep mode. the txd signal has to be logic low during th e mode select window ( figure 4-4 on page 8 ). in sleep mode the transmission path is disabled. supply current from v batt is typically i vssleep =10a. the v cc regulator is switched off; nres and rxd are low. the internal slave termination between pin lin and pin vs is disabled to minimize the power dissipation in case pin lin is short-circuited to gnd. only a weak pull-up current (typically 10 a) between pin lin and pin vs is present. the sleep mode can be activa ted independently from the current level on pin lin. a voltage less than the lin pre-wake detection v linl at pin lin activates the internal lin receiver. a falling edge at the lin pin followed by a dominant bus level maintained for a certain time period (t bus ) and a following rising edge at pin lin respectively results in a remote wake-up request. the device switches fr om sleep mode to fail-safe mode. the v cc regulator is activated, and the internal lin slave termination resistor is switched on. the remote wake-up request is indicat ed by a low level at the rxd pin to interrupt the microcontroller ( figure 4-5 on page 9 ). en high can be used to switch directly from sleep/ silent to fail-safe mode. if en is still high after vcc ramp up and undervoltage reset time, the ic switches to normal mode. figure 4-4. switch to sleep mode delay time sleep mode t d_sleep = maximum 20 s lin switches directly to recessive mode t d = 3.2 s lin vcc nres txd en sleep mode normal mode mode select window
9 4957f?auto?02/08 ATA6623/ata6625 figure 4-5. lin wake-up diagram from sleep mode 4.4 fail-safe mode at system power-up the device automatically sw itches to fail-safe mode. the voltage regulator is switched on (v cc = 3.3v/5v/50 ma), (see figure 6-1 on page 11 ). the nres output switches to low for t res = 4 ms and gives a reset to the microcontroller. lin communication is switched off. the ic stays in this mode until en is switched to high, and changes then to the normal mode. a power down of v batt (v s < 4v) during silent- or sleep mode switches the ic into the fail-safe mode after power up. a logic low at nres switch es the ic into fail-safe mode directly. 4.5 unpowered mode if you connect battery voltage to the application circuit, the voltage at the vs pin increases according to the block capacitor (see figure 6-1 on page 11 ). after vs is higher than the vs undervoltage threshold vs th , the ic mode changes from unpowered mode to fail-safe mode. the vcc output voltage reaches its nominal value after t vcc . this time, t vcc , depends on the vcc capacitor and the load. nres is low for the reset time delay t reset ; no mode change is possible during this time. regulator wake-up time off state on state low fail-safe mode normal mode en high microcontroller start-up time delay reset time low or floating low or floating nres en vcc voltage regulator rxd lin bus bus wake-up filtering time t bus
10 4957f?auto?02/08 ATA6623/ata6625 5. fail-safe features during a short-circuit at lin to v battery , the output limits the output current to i bus_lim . due to the power dissipation, the chip temperature exceeds t linoff and the lin output is switched off. the chip cools down and after a hysteresis of t hys , switches the output on again. rxd stays on high because lin is high. during lin overtemperature switch-off, the v cc regulator is working independently. during a short-circuit from lin to gnd the ic can be switched into sleep or silent mode. if the short-circuit disappears, the ic starts with a remote wake-up. the reverse current is very low < 15 a at pin lin during loss of v batt or gnd. this is optimal behavior for bus systems where some slave nodes are supplied from battery or ignition. during a short circuit at vcc, the output limits the output current to i vccn . because of undervoltage, nres switches to low and sends a reset to the microcontroller. the ic switches into fail-safe mode. if the chip temperature exceeds the value t vccoff , the v cc output switches off. the chip cools down and after a hysteresis of t hys , switches the output on again. because of fail-safe mode, the v cc voltage will switch on again although en is switched off from the microcontroller.the microcontroller can then start with normal operation. pin en provides a pull-down resistor to forc e the transceiver into recessive mode if en is disconnected. pin rxd is set floating if v batt is disconnected. pin txd provides a pull-up resistor to force th e transceiver into recessive mode if txd is disconnected. if txd is short-circuited to gnd, it is possi ble to switch to sleep mode via enable after tdom > 20 ms.
11 4957f?auto?02/08 ATA6623/ata6625 6. voltage regulator figure 6-1. v cc voltage regulator: ra mp up and undervoltage the voltage regulator needs an external capacitor for compensation and to smooth the distur- bances from the microcontroller. it is recommended to use an electrolythic capacitor with c > 10 f and a ceramic capacitor with c = 100 nf. the values of these capacitors can be var- ied by the customer, depending on the application. with this special so8 package (fused lead frame to pin3) an r thja of 80 k/w is achieved. therefore, it is recommended to connect pin 3 with a wide gnd plate on the printed board to get a good heat sink. the main power dissipation of the ic is created from the v cc output current i vcc , which is needed for the application. figure 6-2 shows the safe operating area of the ATA6623/ata6625. nres 5v/3.3v vcc vs 5v/3.3v v thun t res_f t reset t vcc 5.5v/3.8v 12v
12 4957f?auto?02/08 ATA6623/ata6625 figure 6-2. power dissipation: save operating area versus v cc output current and supply voltage v s at different ambient temperatures due to r thja = 80 k/w for programming purposes of the microcontroller it is potentially neccessary to supply the v cc output via an external power supply while the v s pin of the system basis chip is disconnected. this behavior is no problem for the system basis chip. 0.00 8 9 10 11 12 13 14 15 18 19 16 17 567 10.00 20.00 30.00 40.00 50.00 60.00 iout_85: t amb = 85 c iout_105: t amb = 105 c iout_85: t amb = 95 c v s (v) i vcc (ma)
13 4957f?auto?02/08 ATA6623/ata6625 7. absolute maximum ratings stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions beyond t hose indicated in the operational sections of this specification is not implied. exposure to absolute maximum rati ng conditions for extended periods may affect device reliability . parameters symbol min. typ. max. unit supply voltage v s v s ?0.3 +40 v pulse time 500 ms t a =25c output current i vcc 50 ma v s +40 v pulse time 2min t a =25c output current i vcc 50 ma v s 27 v logic pins (rxd, txd, en, nres) ?0.3 +5.5 v output current nres i nres +2 ma lin - dc voltage ?27 +40 v v cc - dc voltage ?0.3 +5.5 v according to ibee lin emc test specification 1.0 following iec 61000-4-2 - pin vs, lin to gnd 6 kv esd hbm following stm5.1 with 1.5 k ? /100 pf - pin vs, lin to gnd 8 kv hbm esd ansi/esd-stm5.1 jesd22-a114 aec-q100 (002) 3 kv cdm esd stm 5.3.1 750 v junction temperature t j ?40 +150 c storage temperature t s ?55 +150 c thermal resistance junction to ambient (free air) r thja 145 k/w special heat sink at gnd (pin 3) on pcb r thja 80 k/w thermal shutdown of v cc regulator t vccoff 150 160 170 c thermal shutdown of lin output t linoff 150 160 170 c thermal shutdown hysteresis t hys 10 c
14 4957f?auto?02/08 ATA6623/ata6625 8. electrical characteristics 5v < v s < 27v, ?40c < t j < 150c; unless otherw ise specified all values refer to gnd pins. no. parameters test conditions pin symbol min. typ. max. unit type* 1 vs pin 1.1 nominal dc voltage range vs v s 513.527 va 1.2 supply current in sleep mode sleep mode v lin > v s ? 0.5v v s < 14v (t j = 25c) vs i vssleep 31014aa sleep mode v lin > v s ? 0.5v v s < 14v (t j = 125c) i vssleep 51116aa 1.3 supply current in silent mode bus recessive v s < 14v (t j = 25c) without load at vcc i vssi 47 57 67 a a bus recessive v s < 14v (t j = 125c) without load at vcc i vssi 56 66 76 a a 1.4 supply current in normal mode bus recessive v s < 14v without load at vcc vs i vsrec 0.3 0.8 ma a 1.5 supply current in normal mode bus dominant v s < 14v v cc load current 50 ma vs i vsdom 50 53 ma a 1.6 v s undervoltage threshold vs v sth 4.0 4.5 5 v a 1.7 vs undervoltage threshold hysteresis vs v sth_hys 0.2 v a 2 rxd output pin 2.1 low level input current normal mode v lin =0v v rxd =0.4v rxd i rxd 1.3 2.5 8 ma a 2.2 low level output voltage i rxd = 1 ma rxd v rxdl 0.4 v a 2.3 internal resistor to v cc rxd r rxd 357k ? a 3 txd input pin 3.1 low level voltage input txd v txdl ?0.3 +0.8 v a 3.2 high level voltage input txd v txdh 2 v cc + 0.3v va 3.3 pull-up resistor v txd =0v txd r txd 125 250 400 k ? a 3.4 high level leakage current v txd =5v txd i txd ?3 +3 a a 4en input pin 4.1 low level voltage input en v enl ?0.3 +0.8 v a 4.2 high level voltage input en v enh 2 v cc + 0.3v va 4.3 pull-down resistor v en = 5v en r en 50 125 200 k ? a 4.4 low level input current v en = 0v en i en ?3 +3 a a *) type means: a = 100% tested, b = 100% correlation tested, c = characterized on samples, d = design parameter
15 4957f?auto?02/08 ATA6623/ata6625 5 nres open drain output pin 5.1 low level output voltage v s 5.5v i nres =1ma i nres = 250 a nres v nresl v nresl 0.2 0.14 v v a a 5.2 low level output low 10 k ? to vcc v cc =0v nres v nresll 0.2 v a 5.3 undervoltage reset time v vs 5.5v c nres =20pf nres t reset 246msa 5.4 reset debounce time for falling edge v vs 5.5v c nres =20pf nres t res_f 1.5 10 s a 6 vcc voltage regulator ATA6623 6.1 output voltage v cc 4v < vs < 18v (0 ma to 50 ma) vcc vcc nor 3.234 3.366 v a 6.2 output voltage v cc at low v s 3v < vs < 4v vcc vcc low v vs ? v drop 3.366 v a 6.3 regulator drop voltage vs > 3v, i vcc = ?15 ma vcc v drop1 200 mv a 6.4 regulator drop voltage vs > 3v, i vcc = ?50 ma vcc v drop2 500 700 mv a 6.5 line regulation maximum 4v < vs < 18v vcc vcc line 1%a 6.6 load regulation maximum 5 ma < i vcc < 50 ma vcc vcc load 0.5 2 % a 6.7 power supply ripple rejection 10 hz to 100 khz c vcc = 10 f vs = 14v, i vcc =?15ma 50 db c 6.8 output current limitation vs > 4v vcc i vccs ?200 ?160 ma a 6.9 load capacity 1 ? < esr < 5 ? @ 100 khz vcc c load 1.8 10 f d 6.10 vcc undervoltage threshold referred to vcc vs > 4v vcc v thunn 2.8 3.2 v a 6.11 hysteresis of undervoltage threshold referred to vcc vs > 4v vcc vhys thun 150 mv a 6.12 ramp up time vs > 4v to vcc = 3.3v c vcc = 2.2 f i load = ?5 ma at vcc vcc t vcc 100 250 s a 7 vcc voltage regulator ata6625 7.1 output voltage v cc 5.5v < vs < 18v (0 ma to 50 ma) vcc vcc nor 4.9 5.1 v a 7.2 output voltage v cc at low v s 4v < vs < 5.5v vcc vcc low v vs ? v d 5.1 v a 7.3 regulator drop voltage vs > 4v, i vcc = ?20 ma vcc v d1 250 mv a 7.4 regulator drop voltage vs > 4v, i vcc = ?50 ma vcc v d2 400 600 mv a 7.5 regulator drop voltage vs > 3.3v, i vcc = ?15 ma vcc v d3 200 mv a 7.6 line regulation maximum 5.5v < vs < 18v vcc vcc line 1%a 8. electrical characteristics (continued) 5v < v s < 27v, ?40c < t j < 150c; unless otherw ise specified all values refer to gnd pins. no. parameters test conditions pin symbol min. typ. max. unit type* *) type means: a = 100% tested, b = 100% correlation tested, c = characterized on samples, d = design parameter
16 4957f?auto?02/08 ATA6623/ata6625 7.7 load regulation maximum 5ma < i vcc < 50 ma vcc vcc load 0.5 2 % a 7.8 output current limitation vs > 5.5v vcc i vccs ?200 ?160 ma a 7.9 load capacity 1 ? < esr < 5 ? @ 100 khz vcc c load 1.8 10 f d 7.10 vcc undervoltage threshold referred to vcc vs > 5.5v vcc v thunn 4.2 4.8 v a 7.11 hysteresis of undervoltage threshold referred to vcc vs > 5.5v vcc vhys thun 250 mv a 7.12 ramp up time vs > 5.5v to vcc = 5v c vcc = 2.2 f i load = ?5 ma at vcc vcc t vcc 130 300 s a 8 lin bus driver: bus load conditions: load 1 (small): 1 nf, 1 k ? ; load 2 (large): 10 nf, 500 ? ; internal pull-up r rxd = 5 k ? ; c rxd = 20 pf 10.5, 10.6 and 10.7 specifies the timing parameters for proper operation at 20 kbps 8.1 driver recessive output voltage load1/load2 lin v busrec 0.9 v s v s va 8.2 driver dominant voltage v vs = 7v r load = 500 ? lin v _losup 1.2 v a 8.3 driver dominant voltage v vs = 18v r load = 500 ? lin v _hisup 2va 8.4 driver dominant voltage v vs = 7v r load = 1000 ? lin v _losup_1k 0.6 v a 8.5 driver dominant voltage v vs = 18v r load = 1000 ? lin v _hisup_1k 0.8 v a 8.6 pull?up resistor to v s the serial diode is mandatory lin r lin 20 30 60 k ? a 8.7 lin current limitation v bus = v batt_max lin i bus_lim 40 120 200 ma a 8.8 input leakage current at the receiver including pull-up resistor as specified input leakage current driver off v bus = 0v v batt = 12v lin i bus_pas_dom ?1 ?0.35 ma a 8.9 leakage current lin recessive driver off 8v < v batt < 18v 8v < v bus < 18v v bus v batt lin i bus_pas_rec 15 20 a a 8.10 leakage current when control unit disconnected from ground. loss of local ground must not affect communication in the residual network gnd device = v s v batt = 12v 0v < v bus < 18v lin i bus_no_gnd ?10 +0.5 +10 a a 8.11 node has to sustain the current that can flow under this condition. bus must remain operational under this condition. v batt disconnected v sup_device = gnd 0v < v bus < 18v lin i bus 515aa 8. electrical characteristics (continued) 5v < v s < 27v, ?40c < t j < 150c; unless otherw ise specified all values refer to gnd pins. no. parameters test conditions pin symbol min. typ. max. unit type* *) type means: a = 100% tested, b = 100% correlation tested, c = characterized on samples, d = design parameter
17 4957f?auto?02/08 ATA6623/ata6625 9 lin bus receiver 9.1 center of receiver threshold v bus_cnt = (v th_dom + v th _ rec )/2 lin v bus_cnt 0.475 v s 0.5 v s 0.525 v s va 9.2 receiver dominant state v en = 5v lin v busdom ?27 0.4 v s va 9.3 receiver recessive state v en = 5v lin v busrec 0.6 v s 40 v a 9.4 receiver input hysteresis v hys = v th_rec ? v th_dom lin v bushys 0.028 v s 0.1 x v s 0.175 v s va 9.5 pre-wake detection lin high level input voltage lin v linh v s ? 1v v s + 0.3v va 9.6 pre-wake detection lin low level input voltage activates the lin receiver lin v linl ?27 v s ? 3.3v v a 10 internal timers 10.1 dominant time for wake?up via lin bus v lin = 0v t bus 30 90 150 s a 10.2 time delay for mode change from pre-normal into normal mode via pin en v en = 5v t norm 520sa 10.3 time delay for mode change from normal mode to sleep mode via pin en v en = 0v t sleep 2 7 15 s a 10.4 txd dominant time out timer v txd = 0v t dom 61320msa 10.5 time delay for mode change from silent mode into normal mode via en v en = 5v t s_n 51540sa 10.6 duty cycle 1 th rec(max) = 0.744 v s th dom(max) = 0.581 v s v s = 7.0v to 18v t bit = 50 s d1 = t bus_rec(min) /(2 t bit ) d1 0.396 a 10.7 duty cycle 2 th rec(min) = 0.422 v s th dom(min) = 0.284 v s v s = 7.6v to 18v t bit = 50 s d2 = t bus_rec(max) /(2 t bit ) d2 0.581 a 10.8 duty cycle 3 th rec(max) = 0.778 v s th dom(max) = 0.616 v s v s = 7.0v to 18v t bit = 96 s d3 = t bus_rec(min) /(2 t bit ) d3 0.417 a 10.9 duty cycle 4 th rec(min) = 0.389 v s th dom(min) = 0.251 v s v s = 7.6v to 18v t bit = 96 s d4 = t bus_rec(max) /(2 t bit ) d4 0.590 a 8. electrical characteristics (continued) 5v < v s < 27v, ?40c < t j < 150c; unless otherw ise specified all values refer to gnd pins. no. parameters test conditions pin symbol min. typ. max. unit type* *) type means: a = 100% tested, b = 100% correlation tested, c = characterized on samples, d = design parameter
18 4957f?auto?02/08 ATA6623/ata6625 figure 8-1. definition of bus timing characteristics 10.10 slope time falling and rising edge at lin v s = 7.0v to 18v t slope_fall t slope_rise 3.5 22.5 s a 11 receiver electrical ac paramete rs of the lin physical layer lin receiver, rxd load cond itions: internal pull-up r rxd = 5 k ? ; c rxd = 20 pf 11.1 propagation delay of receiver figure 8-1 v s = 7.0v to 18v t rx_pd = max(t rx_pdr , t rx_pdf ) t rx_pd 6sa 11.2 symmetry of receiver propagation delay rising edge minus falling edge v s = 7.0v to 18v t rx_sym = t rx_pdr ? t rx_pdf t rx_sym ?2 +2 s a 8. electrical characteristics (continued) 5v < v s < 27v, ?40c < t j < 150c; unless otherw ise specified all values refer to gnd pins. no. parameters test conditions pin symbol min. typ. max. unit type* *) type means: a = 100% tested, b = 100% correlation tested, c = characterized on samples, d = design parameter txd (input to transmitting node) vs (transceiver supply of transmitting node) rxd (output of receiving node1) rxd (output of receiving node2) lin bus signal thresholds of receiving node1 thresholds of receiving node2 t bus_rec(max) t rx_pdr(1) t rx_pdf(2) t rx_pdr(2) t rx_pdf(1) t bus_dom(min) t bus_dom(max) th rec(max) th dom(max) th rec(min) th dom(min) t bus_rec(min) t bit t bit t bit
19 4957f?auto?02/08 ATA6623/ata6625 figure 8-2. application circuit 3 gnd 2 en 6 txd 5 rxd vcc + 100 nf 100 nf 220 pf 10 k ? 10 f 22 f 8 nres 7 short circuit and overtemperature protection normal mode and silent mode 3.3v/50 ma/2% 5v/50 ma/2% control unit normal and fail-safe mode rf filter vcc micro- controller lin vs lin-bus 1 4 txd time-out timer slew rate control undervoltage reset sleep mode vcc switched off wake-up bus timer ATA6623/25 receiver v cc v ba t - + v cc
20 4957f?auto?02/08 ATA6623/ata6625 10. package information 9. ordering information extended type number package remarks ATA6623-tapy so8 3.3v lin system basis chip, pb-free, 1k, taped and reeled ata6625-tapy so8 5v lin system basis chip, pb-free, 1k, taped and reeled ATA6623-taqy so8 3.3v lin system basis chip, pb-free, 4k, taped and reeled ata6625-taqy so8 5v lin system basis chip, pb-free, 4k, taped and reeled package: so 8 dimensions in mm specifications according to din technical drawings issue: 1; 15.08.06 drawing-no.: 6.541-5031.01-4 14 85 0.2 5 0.2 3.8 0.1 6 0.2 3.7 0.1 4.9 0.1 3.81 0.4 1.27 0.1 +0.15 1.4
21 4957f?auto?02/08 ATA6623/ata6625 11. revision history please note that the following page numbers referred to in this section refer to the specific revision mentioned, not to this document. revision no. history 4957f-auto-02/08 ? ?pre-normal mode? in ?fail-safe mode? changed ? section 7 ?absolute maximum ratings? on page 13 changed ? section 8 ?electrical characterist ics? numbers 10.5 to 10.10 on pages 17 to 18 changed 4957e-auto-10/07 ? section 9 ?ordering information? on page 20 changed 4957d-auto-07/07 ? features changed ? block diagram changed ? application diagram changed ? text changed under the headings: 3.2, 3.3, 3.4, 3.6, 3.7, 3.8, 3.9, 4, 4.1, 4. 2, 4.3, 4.4, 4. 5, 5.5, 5.6, 6 ? figure 4-2, 4-3, 4-4, 4-5, 8-2: changed ? figure title 6-1: text changed ? abs. max. ratings: row ?output current nres? added ? el. char. table: values changed in the following rows: 1.3, 5.1, 5.3, 5.4, 6.9, 6. 12, 7.9, 11.1 4957c-auto-02/07 ? features on page 1 changed ? table 2-1 ?pin description? on page 2 changed ? section 3-1 ?physical layer compatibility? on page 3 added ? section 3-2 ?supply pin (vs) on page 3 changed ? section 3-3 ?ground pin (gnd) on page 3 changed ? section 3-8 ?dominant time-out f unction (txd)? on page 4 changed ? section 4-1 ?normal mode? on page 5 changed ? section 4-2 ?silent mode? on page 5 changed ? figure 4-3 ?lin wake-up waveform diagram from silent mode? on page 6 changed ? section 4.3 ?sleep mode? on page 7 changed ? section 4-5 ?unpowered mode? on page 7 changed ? figure 4-4 ?switch to sleep mode? on page 8 changed ? figure 4-6 ?v cc voltage regulator: ramp up and undervoltage? on page 9 changed ? section 5 ?fail-safe features on page 9 changed ? section 6 ?voltage regulator? on page 10 changed ? section 7 ?absolute maximum ratings? on page 11 changed ? section 8 ?electrical characteristics? on pages 12 to 16 changed ? section 9 ?ordering information? on page 18 changed
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